Geneve logical memory map
The logical address map determines which devices or memory areas appear in the logical address space. These are the addresses as seen from the CPU or the program that is run, but they need not correspond to the same physical address at all times. The correspondence is provided by the mapper.
The memory management in Native mode is supported by a XOP call.
The native mode is also called MDOS mode. It is the mode which the Geneve initially boots to, typically with white letters on dark blue, and 80 column display.
|0400||Free space||Onboard memory or expansion|
|F000||On-chip memory 252 bytes||Hides mapped page up to F0FB (see below)|
|F100||Video ports||See below|
|F118||Keyboard||Single address F118 with 8 mirrors|
|F120||Sound chip||Single address F120 with 8 mirrors on even addresses|
|F140||Free space||Onboard memory or expansion|
The on-chip memory of the TMS9995 consists of the address range F000-F0FB and FFFC-FFFF, 256 bytes. The latter four bytes are used for the NMI vector (formerly known as LOAD interrupt vector). The word at FFFA is the decrementer; it may be used as a memory storage when the decrementer is halted.
The memory area is equipped with SRAM at 0 wait states, with full 16 bit access. It is the fastest RAM in the system. Hence, register workspaces should make good use of this area. In that respect, it resembles the Scratch pad RAM of the TI-99/4A.
The on-chip RAM cannot be mapped in or out; it is always present at the specified logical addresses. According to the 9995 specifications, on-chip memory accesses are visible outside; the external address bus is set (only for the even address, as these are full 16-bit accesses), and unspecified data is output on the external data bus on write operations. This means that the hidden RAM is overwritten.
Decoding: 1111 0001 0000 xpp0 (pp = port number; x = don't care)
Addresses are mirrored at position+8 (F100 = F108,...)
|F100 (Port 0)||VRAM||VRAM|
|F102 (Port 1)||Status register||Address counter or video register|
|F104 (Port 2)||-||Palette register|
|F106 (Port 3)||-||Indirect video register access|
The GPL mode is the compatibility mode, which is provided to run TI-99/4A programs.
|0000||GPL interpreter||Operating system|
|2000||Free space 8 KiB||Onboard memory or expansion|
|4000||DSR space||Normally used by the GeneveOS DSR|
|6000||Cartridge ROM contents||Loaded from disk|
|8020||Free space 992 bytes||Also includes the "PAD RAM" (16-bit RAM of the TI-99/4A)|
|8300||Here, its speed depends on SRAM or DRAM mapping|
|8600||External bus||Any device in the PEB that maps to this address|
|9000||Speech synthesizer||if plugged into the PEB|
|A000||Free space 20 KiB|
|F000||On-chip memory||Hides mapped page up to F0FB (see above)|
|F0FC||Free space 3838 bytes|
Decoding: 1000 1wxx xxxx xpp0 (pp = port number; x = don't care; w = write)
Addresses are mirrored 64 times (8800 = 8810 = 8820 = ... 8BF0)
|8800 (Port 0)||VRAM||-|
|8C00 (Port 0)||-||VRAM|
|8802 (Port 1)||Status register||-|
|8C02 (Port 1)||-||Address counter or video register|
|8C04 (Port 2)||-||Palette register|
|8C06 (Port 3)||-||Indirect video register access|