Difference between revisions of "Instruction Set of all TMS99xxx CPUs"

From Ninerpedia
Jump to navigation Jump to search
(minor border fixes)
(Correct opcode for LIIM)
 
(One intermediate revision by the same user not shown)
Line 134: Line 134:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">AR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">AR</tt>*
|| <BR>
|| 6
|| 0C40
|| 0C40
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 01ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 01ss SSSS</tt>
Line 168: Line 168:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">BIND</tt>
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">BIND</tt>
|| <BR>
|| 6
|| 0140
|| 0140
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 01ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 01ss SSSS</tt>
Line 270: Line 270:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CER</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CER</tt>*
|| <BR>
|| 7
|| 0C06
|| 0C06
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0110</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0110</tt>
Line 304: Line 304:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CIR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CIR</tt>*
|| <BR>
|| 6
|| 0C80
|| 0C80
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 10ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 10ss SSSS</tt>
Line 406: Line 406:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CRE</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CRE</tt>*
|| <BR>
|| 7
|| 0C04
|| 0C04
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0100</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0100</tt>
Line 423: Line 423:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CRI</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">CRI</tt>*
|| <BR>
|| 7
|| 0C00
|| 0C00
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0000</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0000</tt>
Line 542: Line 542:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER
| HEIGHT=34 ALIGN=LEFT style="white-space:nowrap; font-size:80%" | <tt style="font-size:140%">DIVS</tt> (ST4=1)<BR><tt style="font-size:140%">DIVS</tt> (ST4=0)
| HEIGHT=34 ALIGN=LEFT style="white-space:nowrap; font-size:80%" | <tt style="font-size:140%">DIVS</tt> (ST4=1)<BR><tt style="font-size:140%">DIVS</tt> (ST4=0)
|| <BR>
|| 6
|| 0180
|| 0180
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 10ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 10ss SSSS</tt>
Line 559: Line 559:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">DR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">DR</tt>*
|| <BR>
|| 6
|| 0D40
|| 0D40
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 01ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 01ss SSSS</tt>
Line 576: Line 576:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">EVAD</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">EVAD</tt>*
|| <BR>
|| 6
|| 0100
|| 0100
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 00ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 00ss SSSS</tt>
Line 899: Line 899:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LDD</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LDD</tt>*
|| <BR>
|| 7
|| 07C0
|| 07C0
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0111 1100 0000</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0111 1100 0000</tt>
Line 916: Line 916:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LDS</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LDS</tt>*
|| <BR>
|| 7
|| 0780
|| 0780
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0111 1000 0000</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0111 1000 0000</tt>
Line 951: Line 951:
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LIIM</tt>
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LIIM</tt>
|| 9
|| 9
|| 2C00
|| 2C80
| style="white-space: nowrap" | <tt style="font-size:110%">0010 1100 1xxx xxii</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0010 1100 1xxx xxii</tt>
| STYLE="border-left: 1px solid black" | <BR>
| STYLE="border-left: 1px solid black" | <BR>
Line 1,001: Line 1,001:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">LR</tt>*
|| <BR>
|| 6
|| 0D80
|| 0D80
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 10ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 10ss SSSS</tt>
Line 1,154: Line 1,154:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">MPYS</tt>
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">MPYS</tt>
|| <BR>
|| 6
|| 01C0
|| 01C0
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 11ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 0001 11ss SSSS</tt>
Line 1,171: Line 1,171:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">MR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">MR</tt>*
|| <BR>
|| 6
|| 0D00
|| 0D00
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 00ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 00ss SSSS</tt>
Line 1,205: Line 1,205:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">NEGR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">NEGR</tt>*
|| <BR>
|| 7
|| 0C02
|| 0C02
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0010</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 0000 0010</tt>
Line 1,443: Line 1,443:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">SR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">SR</tt>*
|| <BR>
|| 6
|| 0CC0
|| 0CC0
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 11ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1100 11ss SSSS</tt>
Line 1,545: Line 1,545:
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
|- style="border-bottom: 1px solid lightgray" VALIGN=TOP ALIGN=CENTER HEIGHT=19
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">STR</tt>*
| ALIGN=LEFT style="white-space: nowrap" | <tt style="font-size:110%">STR</tt>*
|| <BR>
|| 6
|| 0DC0
|| 0DC0
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 11ss SSSS</tt>
| style="white-space: nowrap" | <tt style="font-size:110%">0000 1101 11ss SSSS</tt>

Latest revision as of 12:26, 5 September 2015

This is a comparative table which lists all assembly instructions for each TMS99xxx processor.

9900 9995 99105 99110 9980/81 9940
Mnemonic Format op code binary C M C M C M C M C M C M
A 1 A000 1010 ddDD DDss SSSS 14 4 8 8 4 4 4 4 22 8 X
AB 1 B000 1011 ddDD DDss SSSS 14 4 5 5 4 4 4 4 22 8 X
ABS (MSB=0)
ABS (MSB=1)
6 0740 0000 0111 01ss SSSS 12
14
2
3
6 6 5 3 5 3 16
20
4
6
X
AI 8 0220 0000 0010 0010 RRRR 14 4 8 8 4 4 4 4 22 8 X
AM*
002A
4000
0000 0000 0010 1010
0100 ddDD DDss SSSS






12 8



ANDI 8 0240 0000 0010 0100 RRRR 14 4 8 8 4 4 4 4 22 8 X
AR* 6 0C40 0000 1100 01ss SSSS





u u



B 6 0440 0000 0100 01ss SSSS 8 2 4 2 3 1 3 1 12 4 X
BIND 6 0140 0000 0001 01ss SSSS



4 2 4 2



BL 6 0680 0000 0110 01ss SSSS 12 3 7 4 5 2 5 2 18 6 X
BLSK 8 00B0 0000 0000 1011 RRRR



7 5 7 5



BLWP 6 0400 0000 0100 00ss SSSS 26 6 17 12 10 6 10 6 38 12 X
C 1 8000 1000 ddDD DDss SSSS 14 3 7 6 4 3 4 3 20 6 X
CB 1 9000 1001 ddDD DDss SSSS 14 3 5 4 4 3 4 3 20 6 X
CER* 7 0C06 0000 1100 0000 0110





u u



CI 8 0280 0000 0010 1000 RRRR 14 3 7 6 4 3 4 3 20 6 X
CIR* 6 0C80 0000 1100 10ss SSSS





u u



CKOF 7 03C0 0000 0011 1100 0000 12 1 8 2 9 1 9 1 14 2

CKON 7 03A0 0000 0011 1010 0000 12 1 8 2 9 1 9 1 14 2

CLR 6 04C0 0000 0100 11ss SSSS 10 3 5 4 3 2 3 2 16 6 X
COC 3 2000 0010 00DD DDss SSSS 14 3 7 6 4 3 4 3 20 6 X
CR*
0301
0000
0000 0011 0000 0001
0000 ddDD DDss SSSS






u u



CRE* 7 0C04 0000 1100 0000 0100





u u



CRI* 7 0C00 0000 1100 0000 0000





u u



CZC 3 2400 0010 01DD DDss SSSS 14 3 7 6 4 3 4 3 20 6 X
DCA 9 2C00 0010 1100 00ss SSSS









7
DCS 9 2C40 0010 1100 01ss SSSS









7
DEC 6 0600 0000 0110 00ss SSSS 10 3 6 6 3 3 3 3 16 6 X
DECT 6 0640 0000 0110 01ss SSSS 10 3 6 6 3 3 3 3 16 6 X
DIV (ST4=1)
DIV (ST4=0)
9 3C00 0011 11DD DDss SSSS 16
92-124
3
6
10
34
8
12
6/10
30
4
6
6/10
30
4
6
22
104-136
6
12
X
DIVS (ST4=1)
DIVS (ST4=0)
6 0180 0000 0001 10ss SSSS

36
39
8
12
10/13/33
34
4
6
10/13/33
34
4
6




DR* 6 0D40 0000 1101 01ss SSSS





u u



EVAD* 6 0100 0000 0001 00ss SSSS





u u



IDLE 7 0340 0000 0011 0100 0000 12 1 8+2*I 2 9+2*N 1 9+2*N 1 14 2 X
INC 6 0580 0000 0101 10ss SSSS 10 3 6 6 3 3 3 3 16 6 X
INCT 6 05C0 0000 0101 11ss SSSS 10 3 6 6 3 3 3 3 16 6 X
INV 6 0540 0000 0101 01ss SSSS 10 3 6 6 3 3 3 3 16 6 X
JEQ (cnd is true)
(cnd is not true)
2 1300 0001 0011 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JGT (cnd is true)
(cnd is not true)
2 1500 0001 0101 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JH (cnd is true)
(cnd is not true)
2 1B00 0001 1011 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JHE (cnd is true)
(cnd is not true)
2 1400 0001 0100 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JL (cnd is true)
(cnd is not true)
2 1A00 0001 1010 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JLE (cnd is true)
(cnd is not true)
2 1200 0001 0010 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JLT (cnd is true)
(cnd is not true)
2 1100 0001 0001 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JMP (cnd is true)
(cnd is not true)
2 1000 0001 0000 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JNC (cnd is true)
(cnd is not true)
2 1700 0001 0111 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JNE (cnd is true)
(cnd is not true)
2 1600 0001 0110 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JNO (cnd is true)
(cnd is not true)
2 1900 0001 1001 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JOC (cnd is true)
(cnd is not true)
2 1800 0001 1000 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
JOP (cnd is true)
(cnd is not true)
2 1C00 0001 1100 CCCC CCCC 10
8
1
1
4
4
2
2
3 1 3 1 12
10
2
2
X
LDCR (C=0)
LDCR (C≠0)
(MSB R12=1, autoinc.)
(MSB R12=1, no autoinc.)
4 3000 0011 00CC CCss SSSS 52
20+2*C
3
3
44
12+2*C
6
6
40
8+2*cnt
8
8
3
3
4
3
40
8+2*cnt
8
8
3
3
4
3
58
26+2*C
6
6
X
LDD* 7 07C0 0000 0111 1100 0000





u u



LDS* 7 0780 0000 0111 1000 0000





u u



LI 8 0200 0000 0010 0000 RRRR 12 3 6 6 3 3 3 3 18 6 X
LIIM 9 2C80 0010 1100 1xxx xxii









10
LIMI 8 0300 0000 0011 0000 0000 16 2 7 4 5 2 5 2 22 6 X
LMF






u u u u



LR* 6 0D80 0000 1101 10ss SSSS





u u



LREX 7 03E0 0000 0011 1110 0000 12 1 8 2 9 1 9 1 14 2

LST 8 0080 0000 0000 1000 RRRR

7 4 7 2 7 2



LWP 8 0090 0000 0000 1001 RRRR

6 4 3 2 3 2



LWPI 8 02E0 0000 0010 1110 0000 10 2 6 4 3 2 3 2 14 4 X
MM*
0302
0000
0000 0011 0000 0010
0000 ddDD DDss SSSS






u u



MOV 1 C000 1100 ddDD DDss SSSS 14 4 6 6 3 3 3 3 22 8 X
MOVB 1 D000 1101 ddDD DDss SSSS 14 4 4 4 4 4 4 4 22 8 X
MPY 9 3800 0011 10DD DDss SSSS 52 5 28
29
10
12
23 5 23 5 62 10 X
MPYS 6 01C0 0000 0001 11ss SSSS

30 10 25 5 25 5



MR* 6 0D00 0000 1101 00ss SSSS





u u



NEG 6 0500 0000 0101 00ss SSSS 12 3 6 6 3 3 3 3 18 6 X
NEGR* 7 0C02 0000 1100 0000 0010





u u



ORI 8 0260 0000 0010 0110 RRRR 14 4 8 8 4 4 4 4 22 8 X
RSET 7 0360 0000 0011 0110 0000 12 1 8 2 9 1 9 1 14 2

RTWP 7 0380 0000 0011 1000 0000 14 4 10 8 9/7 4 9/7 4 22 8 X
S 1 6000 0110 ddDD DDss SSSS 14 4 8 8 4 4 4 4 22 8 X
SB 1 7000 0111 ddDD DDss SSSS 14 4 5 5 4 4 4 4 22 8 X
SBO 2 1D00 0001 1101 CCCC CCCC 12 2 10 4 7 2 7 2 16 4 X
SBZ 2 1E00 0001 1110 CCCC CCCC 12 2 10 4 7 2 7 2 16 4 X
SETO 6 0700 0000 0111 00ss SSSS 10 3 5 4 3 2 3 2 16 6 X
SLA (C≠0)
(C=0, R0 bit 12-15=0)
(C=0, R0 bit 12-15=N≠0)
5 0A00 0000 1010 CCCC SSSS 12+2*C
52
20+2*N
3
4
4
8+C
27
11+N
6
8
8
5+SC
23
7+SC
3
4
4
5+SC
23
7+SC
3
4
4
18+2*C
60
28+2*N
6
8
8
X
SLAM* (C=0)
SLAM* (C≠0)

001D
4000
0000 0000 0001 1101
0100 00CC CCss SSSS






11+SC
13+SC
5
6




SM*
0029
4000
0000 0000 0010 1001
0100 ddDD DDss SSSS






12 7



SOC 1 E000 1110 ddDD DDss SSSS 14 4 8 8 4 4 4 4 22 8 X
SOCB 1 F000 1111 ddDD DDss SSSS 14 4 5 5 4 4 4 4 22 8 X
SR* 6 0CC0 0000 1100 11ss SSSS





u u



SRA (C≠0)
(C=0, R0 bit 12-15=0)
(C=0, R0 bit 12-15=N≠0)
5 0800 0000 1000 CCCC SSSS 12+2*C
52
20+2*N
3
4
4
8+C
27
11+N
6
8
8
5+SC
23
7+SC
3
4
4
5+SC
23
7+SC
3
4
4
18+2*C
60
28+2*N
6
8
8
X
SRAM* (C=0)
SRAM* (C≠0)

001C
4000
0000 0000 0001 1100
0100 00CC CCss SSSS






11+SC
13+SC
5
6




SRC (C≠0)
(C=0, R0 bit 12-15=0)
(C=0, R0 bit 12-15=N≠0)
5 0B00 0000 1011 CCCC SSSS 12+2*C
52
20+2*N
3
4
4
8+C
27
11+N
6
8
8
5+SC
23
7+SC
3
4
4
5+SC
23
7+SC
3
4
4
18+2*C
60
28+2*N
6
8
8
X
SRL (C≠0)
(C=0, R0 bit 12-15=0)
(C=0, R0 bit 12-15=N≠0)
5 0900 0000 1001 CCCC SSSS 12+2*C
52
20+2*N
3
4
4
8+C
27
11+N
6
8
8
5+SC
23
7+SC
3
4
4
5+SC
23
7+SC
3
4
4
18+2*C
60
28+2*N
6
8
8
X
STCR (C=0)
STCR (1≤C≤7)
STCR (C=8)
STCR (9≤C≤15)
(MSB R12=1, autoinc.)
(MSB R12=1, no autoinc.)
4 3400 0011 01CC CCss SSSS 60
42
44
58
4
4
4
4
47
23+C
23+C
31+C
8
8
8
8
43
20+cnt
27
20+cnt
10
10
3
4
4
3
5
4
43
20+cnt
27
20+cnt
10
10
3
4
4
3
5
4
68
50
52
66
8
8
8
8
X
STR* 6 0DC0 0000 1101 11ss SSSS





u u



STST 8 02C0 0000 0010 1100 RRRR 8 2 5 4 3 2 3 2 12 4 X
STWP 8 02A0 0000 0010 1010 RRRR 8 2 5 4 3 2 3 2 12 4 X
SWPB 6 06C0 0000 0110 11ss SSSS 10 3 16 6 3 3 3 3 16 6 X
SZC 1 4000 0100 ddDD DDss SSSS 14 4 8 8 4 4 4 4 22 8 X
SZCB 1 5000 0101 ddDD DDss SSSS 14 4 5 5 4 4 4 4 22 8 X
TB 2 1F00 0001 1111 CCCC CCCC 12 2 10 4 7 2 7 2 16 4 X
TCMB*
0C0A
0000
0000 1100 0000 1010
0000 00CC CCss SSSS






26 3



TMB*
0C09
0000
0000 1100 0000 1001
0000 00CC CCss SSSS






26 3



TSMB*
0C0B
0000
0000 1100 0000 1011
0000 00CC CCss SSSS






26 3



X 6 0480 0000 0100 10ss SSSS 8 2 4 4 2 1 2 1 12 4 X
XOP 9 2C00 0010 11DD DDss SSSS 36 8 22 14 14 7 14 7 52 16 X
XOR 3 2800 0010 10CC CCss SSSS 14 4 8 8 4 4 4 4 22 8 X
* = Macrostore Instruction
(two word instruction)


C = constant value bit
d = Dest. address mode bit
D = Dest. operand bit
s = Source address mode bit
S = Source operand bit
R = Workspace register number
i = Interrupt mask bit
x = Don't care


u = unknown u = unknown
X = see 9900