Difference between revisions of "Geneve physical memory map"

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=== Boot EPROM space ===
 
=== Boot EPROM space ===
  
The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the [[PFM]].
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The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the [[Programmable Flash Memory Expansion | PFM]].
  
 
On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.
 
On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.

Revision as of 15:14, 27 January 2021

The physical memory map declares which physical addresses are used to access memory regions or devices.

Native mode

Memory map

Address Banks Region
000000 00-3F 512 KiB On-board DRAM Slow RAM (1 ws)
080000 40-7F 512 KiB On-board DRAM expansion Allocated, but technically infeasible (no sockets or signal lines)
100000 80-B7 448 KiB P-Box space May be used by MEMEX card
170000 B8-BF 64 KiB P-Box space Used by current expansion cards
180000 C0-E7 Future SRAM expansion Only in P-Box
1D0000 E8-EB 32 KiB On-board SRAM expansion Soldered on top of the existing 32 KiB chip
1D8000 EC-EF 32 KiB On-board SRAM Original SRAM memory (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Memory expansions

The bank area 40-7F is assigned to a "Future on-board memory expansion". In fact, the external bus (to the PEB) is not activated during accesses in that area, which means that external cards cannot populate this space. However, the Geneve main board does not offer sockets for such additional on-board memory. It is not possible to add these chips on top of the existing DRAM chips either. The only way to make use of this area is by using the MEMEX in a Genmod configuration.

The bank area C0-E7 is assigned to SRAM (0 ws) fast memory. For accesses in that area, the external bus is activated, which means that SRAM chips for that area must be put on a card that plugs into the PEB.

Boot EPROM space

The Boot EPROM region may have up to 128 KiB space as 16 banks of 8 KiB. This is used with the PFM.

On reset, bank F8 is mapped into the 0000-1FFF logical address region. The EPROM on the stock Geneve defines all even banks as mirrors of F0, and all odd banks as mirrors of F1.

GPL mode

Memory map

Address Banks Region
000000 00-35 432 KiB On-board DRAM Slow RAM (1 ws)
06C000 36 8 KiB Cartridge ROM space (bank 1) First bank of cartridge (Extended Basic style)
06E000 37 8 KiB Cartridge ROM space (bank 2) Second bank of cartridge (Extended Basic style)
070000 38-3F 64 KiB GRAM Cartridge space Mapper byte 06 must be set to 0x03 to enable GROM/GRAM
080000 40-7F 512 KiB On-board DRAM expansion Allocated, but technically infeasible (no sockets or signal lines)
100000 80-B7 448 KiB P-Box space May be used by MEMEX card
170000 B8-BF 64 KiB P-Box space Used by current expansion cards
180000 C0-E7 Future SRAM expansion Only in P-Box
1D0000 E8-EB 32 KiB On-board SRAM expansion Soldered on top of the existing 32 KiB chip
1D8000 EC-EF 32 KiB On-board SRAM Original SRAM memory (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Cartridge emulation

The cartridge emulation in the Gate array shows some peculiarities.

  • The mapper byte 06 (F116 / 8006) must be set to 03 to enable the GROM/GRAM cartridge space. Otherwise, no GROM/GRAM handling is emulated.
  • In GPL mode, logical addresses 6000-7FFF are always mapped to bank 36/37, regardless of the mapper byte 03 (F113 / 8003).
  • CRU address 1EF8 is used to switch between single or dual bank cartridge ROM. When set to 0, only bank 36 is used. When set to 1, writing to cartridge space addresses 6000 + n*4 selects bank 36, while writing to 6002 + n*4 selects bank 37.
  • Cartridge GRAM regions are 8 KiB large, unlike real GROMs with 6 KiB.
  • Address wrapping occurs at 8K boundaries (3FFF+1 = 2000).
  • Reading via the GROM read address delivers the byte at the current GROM address, then advances the address by 1. Writing puts the byte at the current address, then advances the address by 1.
  • Reading the GROM address pointer delivers the MSB, then on every subsequent read access the LSB. The counter contains the former LSB in both bytes after reading and must be restored.

Genmod

The Genmod (Geneve modification) can be run in two modes, selectable by a switch. The TI mode activates the on-board slow DRAM, which is required to run the GPL mode. The reason is that the Gate array maps the GROM accesses to the DRAM on the board, which cannot be changed to the external RAM.

TI mode

Address Banks Region
000000 00-35 432 KiB On-board DRAM Slow RAM (1 ws)
06C000 36 8 KiB Cartridge ROM space (bank 1) First bank of cartridge (Extended Basic style)
06E000 37 8 KiB Cartridge ROM space (bank 2) Second bank of cartridge (Extended Basic style)
070000 38-3F 64 KiB GRAM Cartridge space Map byte 06 must be set to 0x03 to enable GRAM
080000 40-EF 1408 KiB P-Box memory expansion (MEMEX) SRAM (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored

Non-TI mode

Address Banks Region
000000 00-EF 1920 KiB P-Box memory expansion (MEMEX) SRAM (0 ws)
1E0000 F0-FF 128 KiB Boot EPROM Originally, only 16 KiB installed at F0,F1; mirrored