Difference between revisions of "Geneve GPL Interpreter"
| Line 1: | Line 1: | ||
== Mapping == | |||
For Speed 5 and MDOS DSR: | |||
{| class="plainc" | |||
|- | |||
! Page for 0000-1FFF | |||
! Page for 2000-3FFF | |||
! Page for 4000-5FFF | |||
! Page for 6000-7FFF | |||
! Page for 8000-9FFF | |||
! Page for A000-BFFF | |||
! Page for C000-DFFF | |||
! Page for E000-FFFF | |||
|- | |||
| EC | |||
| ED | |||
| 07 | |||
| 34 | |||
| EE | |||
| EF | |||
| 03 | |||
| 53 | |||
|} | |||
For different speeds different kinds of RAM (DRAM vs. SRAM) are used. The ROMPAGE feature sets the 4000-5FFF page value to >BA, which points to the address space of the peripheral card in the box, unlike >07 which contains the MDOS replacement DSR. | |||
== Speed selection == | == Speed selection == | ||
| Line 5: | Line 32: | ||
{| class="plainc" | {| class="plainc" | ||
|- | |- | ||
! | ! Speed | ||
! | ! Video waitstates | ||
! | ! Extra waitstates | ||
! | ! Page for 0000-1FFF | ||
! | ! Page for 8000-9FFF | ||
|- | |- | ||
| 1 | | 1 | ||
| Line 42: | Line 69: | ||
|- | |- | ||
|} | |} | ||
The memory pages EC, ED, EE, and EF are SRAM pages with 0 waitstate access. Other pages are DRAM pages with one waitstate. Thus, the speed is controlled by waitstates in the GPL interpreter (locations 0000-1FFF) and in the PAD RAM (8300-83FF), which is '''not''' the high speed [[on-chip RAM]] of the TMS9995 processor (which is always located at F000, regardless of the mapper value). | |||
[[Category:Geneve]] | [[Category:Geneve]] | ||
Revision as of 12:15, 17 October 2011
Mapping
For Speed 5 and MDOS DSR:
| Page for 0000-1FFF | Page for 2000-3FFF | Page for 4000-5FFF | Page for 6000-7FFF | Page for 8000-9FFF | Page for A000-BFFF | Page for C000-DFFF | Page for E000-FFFF |
|---|---|---|---|---|---|---|---|
| EC | ED | 07 | 34 | EE | EF | 03 | 53 |
For different speeds different kinds of RAM (DRAM vs. SRAM) are used. The ROMPAGE feature sets the 4000-5FFF page value to >BA, which points to the address space of the peripheral card in the box, unlike >07 which contains the MDOS replacement DSR.
Speed selection
The GPL Interpreter allows for selecting the execution speed. Five speeds are selectable. The speed is determined by these settings:
| Speed | Video waitstates | Extra waitstates | Page for 0000-1FFF | Page for 8000-9FFF |
|---|---|---|---|---|
| 1 | x | x | EC | 34 |
| 2 | x | - | 33 | 34 |
| 3 | x | - | EC | 34 |
| 4 | x | - | 33 | EE |
| 5 | x | - | EC | EE |
The memory pages EC, ED, EE, and EF are SRAM pages with 0 waitstate access. Other pages are DRAM pages with one waitstate. Thus, the speed is controlled by waitstates in the GPL interpreter (locations 0000-1FFF) and in the PAD RAM (8300-83FF), which is not the high speed on-chip RAM of the TMS9995 processor (which is always located at F000, regardless of the mapper value).