Difference between revisions of "Geneve CRU definitions"

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Line 14: Line 14:
|-
|-
| 0006
| 0006
| Joystick (button?)
| Joystick button
|-
|-
| 0008
| 0008
Line 30: Line 30:
| 0010
| 0010
| Keyboard Interrupt
| Keyboard Interrupt
|-
| 0012
| (H, mirrors 003a)
|-
| 0014
| (Mouse button, mirrors 0038)
|-
| 0016
| -
|-
|-
| 0018
| 0018
| INTB
| INTB, mirrors 0034
|-
|-
| 001a
| 001a
| Real-Time clock interrupt
| -  
|-
| 001c
| -
|-
| 001e
| -
|-
| 0020
| P-Box reset line
|-
| 0022
| VDP reset
|-
|-
| 0024
| 0024
| Joystick select
| Joystick select
|-
| 0026
| -
|-
| 0028
| -
|-
| 002a
| -
|-
|-
| 002c
| 002c
Line 47: Line 77:
|-  
|-  
| 0030
| 0030
| P-Box reset
| -
|-  
|-  
| 0032
| 0032
Line 53: Line 83:
|-  
|-  
| 0034
| 0034
| P-Box pin 18 sense (declared as not used)
| P-Box INTB
|-  
|-  
| 0036
| 0036
Line 62: Line 92:
|-  
|-  
| 003a
| 003a
| VDP reset
| H
|-
| 003c
| (Keyboard interrupt, mirrors 0010)
|-  
|-  
| 003e
| (Joystick up, mirrors 000e)
|}
|}



Revision as of 23:37, 17 September 2011

Definitions

/signal means negative logic

TMS 9901
0002 INTA
0004 VDP Interrupt
0006 Joystick button
0008 Joystick left
000a Joystick right
000c Joystick down
000e Joystick up
0010 Keyboard Interrupt
0012 (H, mirrors 003a)
0014 (Mouse button, mirrors 0038)
0016 -
0018 INTB, mirrors 0034
001a -
001c -
001e -
0020 P-Box reset line
0022 VDP reset
0024 Joystick select
0026 -
0028 -
002a -
002c Keyboard reset
002e /VDP wait states
0030 -
0032 System clock speed
0034 P-Box INTB
0036 External memory cycle select
0038 Mouse button 3
003a H
003c (Keyboard interrupt, mirrors 0010)
003e (Joystick up, mirrors 000e)
Special
13c0-13fe Single step
TMS9995
1ee0 Decrementer in event counter mode (0=in timer mode)
1ee2 Enable decrementer
1ee4 Interrupt level 1 latch
1ee6 Interrupt level 2 latch
1ee8 Interrupt level 4 latch
1eea-1eee not used
1ef0 Keyboard clock enable
1ef2 Clear keyboard input register
1ef4 Geneve mode (/TI mode)
1ef6 Direct mode (/Mapper mode)
1ef8 Cartridge rom size (1=8 KiB, 0=16 Kib)
1efa /Protect 6xxx
1efc /Protect 7xxx
1efe /Add wait state per memory cycle
1fda Macro Instruction Detect

The MID flag is set whenever the CPU encounters an unknown opcode. This (together with the interrupt) may be used to implement new "commands" on the application level.

Usage

As always, CRU bits are queried and set with special commands. Bits are addressed as offsets to a base address which is stored in Workspace Register 12 (R12). The base address is stored in bits 3-14, so the R12 value is twice as high as the absolute bit address. (Note that bit 15 cannot be used since A15 and CRUOUT share the same line.) Base addresses are commonly noted as register 12 values.

Turn on Geneve mode:

LI   R12,>1EF4
SBO  0

or, equivalently

LI   R12,>1EE0
SBO  10

since 0x1ee0 + 10*2 = 0x1ee0 + 0x14

(bit numbers are often given in decimal notation)

The LDCR and STCR commands are used to write or read multiple CRU bits. The base address is automatically incremented for each bit transfer. Bit transfers begin at the least significant bit. Note that it is relevant whether less than 9 bits are transferred: If less, the memory location is treated as a byte address, if more, as a word address.

LI   R12,>0006
STCR R0,5

reads the five joystick lines, storing the bits in the least significant five bits of the high byte of R0, with bit 3 at the right.

x x x up down right left but x x x x x x x x

If we had transferred 9 bits, all bits as shown above are shifted to the right by 8 positions (starting at the very right bit).

LI   R12,>1EF0
LI   R1,>f100   * binary: 11110001
LCDR R1,8

This enables the keyboard clock, not clearing the input register, activating TI mode and mapping, cartridges have 8K, no write protection to 6xxx and 7xxx, and no wait states.