View source for SSSD Format Log

This is a transcript of a formatting procedure with Disk Manager 2 and a single-sided, single-density diskette. We can find the commands written to the command register of the controller chip (FD1771), the data written to the other registers, and data read from the registers.

There are several phases in this format procedure:

* Attempt to read the inserted disk
* The user provides some parameters using a screen input mask
* Formatting starts by writing 40 tracks
* Then a verify phase is performed, reading all sectors on the disk
* The headers are written and shown on the screen.

This log especially shows how a track looks like that is written to the disk in FM mode. There are a lot of additional bytes outside of the sectors which are used to define the track structure. Due to the architecture of the FD1771, the bytes as shown here are not always the bytes as they will be found on the medium. For instance, writing an 0xf7 byte causes the controller to write a 16-bit CRC word onto the disk. 

 /* Formatting log.
 
    c = command register
    s = sector register
    t = track register
    d or plain number = data register 
 
    st? = get status register
    s? = get sector register
    t? = get track register
    ? = get data register
 */
 
 
 c=d0 (FORCE INTERRUPT, TERMINATE WITH NO INTERRUPT)
 st?=02
 st?=00
 
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05 (TRACK 0, BUSY)
 st?=05 
 st?=04 (TRACK 0)
 st?=04 
 
 /* Try to read the VIB */
 t=00 (track 0)
 st?=04
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=05
 st?=04
 st?=04
 
 d=00 
 s=00 (sector 0)
 t?=00
 st?=04
 
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 00 01 5b d5 (TRACK 0, SIDE 0, SECTOR 0, LENGTH 256, CRC 5bd5)
 st?=00
 
 s=00 (sector 0)
 st?=00
 c=88 (READ SECTOR, SINGLE, DONT CHECK FOR SIDE, NO DELAY)
 ?4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 st?=00
 st?=00

Next: Format all 40 tracks. '''Important:''' The TI Floppy Disk Controller has a bug in the format routine at address >442C where it uses a MOVB command instead of a MOV. This causes an offset of the pointer into VDP RAM which does not precisely point to the beginning of the track anymore, but 9 bytes before. These bytes are written by previous operations and are actually violating the standard track format. You can find the bytes as "7f 3f ... 01". Accordingly, the track ends early, but the ending bytes are only put there to make the controller time out which obviously succeeds with less bytes as well.

So the correct format would start with 16+6 times >00 and ends with 45+231 times >ff. And there is another issue: The track length should be >0CA3 bytes long, but in the loop the controller writes two bytes and decrements by two, so we get one additional byte at the end.

 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=05
 st?=04
 st?=04
 st?=04
 
 c=f4 (WRITE TRACK, DELAY 15ms)
 st?=02
 st?=02
 
 7f 3f 00 cf e0 7f 3f 01 01    (false bytes)
 
 00*16
 
 00 00 00 00 00 00 
 fe
 00 00 00
 01
 f7
 ff*11
 00 00 00 00 00 00
 fb
 e5*256
 f7
 ff*45
 
 00 00 00 00 00 00 
 fe 
 00 00 07 
 01 
 f7 
 ff*11
 00 00 00 00 00 00 
 fb 
 e5*256
 f7 
 ff*45
 
 00 00 00 00 00 00
 fe
 00 00 05
 01
 f7
 ff*11
 00 00 00 00 00 00
 fb
 e5*256 
 f7
 ff*45
 
 ... (skipping) ...
 
 00 00 00 00 00 00
 fe
 00 00 02
 01
 f7
 ff*11
 00 00 00 00 00 00
 fb
 e5*256
 f7
 ff*45
 ff*222 (TIMEOUT)
 
 ff (overly) 
 
 c=5a (STEP IN, UPDATE TR, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=01 (BUSY)
 st?=21 (BUSY, HEAD LOADED)
 st?=20 (HEAD LOADED)
 st?=20 (HEAD LOADED)
 
 ... (skipping) ...
 
 c=f4 (WRITE TRACK, DELAY 15ms)
 st?=02 (DR EMPTY)
 st?=02 (DR EMPTY)
 
 7f 3f 00 cf e0 7f 3f 01 01
 
 00*16
 
 00 00 00 00 00 00 
 fe
 27 00 00
 01
 f7
 ff*11
 00 00 00 00 00 00
 fb
 e5*256
 f7
 ff*45
 
 ... (skipping) ...
 
 00 00 00 00 00 00
 fe
 27 00 02
 01
 f7
 ff*11
 00 00 00 00 00 00
 fb
 e5*256
 f7
 ff*45
 ff*222
 
 ff 
 
 c=5a (STEP IN, UPDATE TR, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=01
 st?=21
 st?=20

All tracks are now formatted. Return to sector 0 and write the Volume information block and the File descriptor index record. When a sector is written, try to read it afterwards (this considerably slows down writing).
 
 /* Write the VIB */
 t=00 (track 0)
 st?=20
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05 (TRACK 0, BUSY)
 st?=25 (HEAD LOADED, TRACK 0, BUSY)
 st?=24 (HEAD LOADED, TRACK 0)
 st?=24
 
 d=00 
 s=00 (sector 0)
 t?=00
 st?=24
 
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 00 01 5b d5 (TRACK 0, SIDE 0, SECTOR 0, LENGTH 256, CRC 5bd5)
 st?=00
 
 s=00 (sector 0)
 st?=00
 c=a8 (WRITE SECTOR, SINGLE RECORD, DONT CHECK SIDE, DAM=FB)
 4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 st?=00
 st?=00
 
 c=88 (READ SECTOR, SINGLE) /* verify */
 ?4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 st?=00
 
 /* Write the File Descriptor Index Record */
 t=00
 st?=00
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=25
 st?=24
 st?=24
 
 d=00 
 s=01 (sector 1)
 t?=00
 st?=24
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 01 01 6e e4 (TRACK 0, SIDE 0, SECTOR 1, LENGTH 256, CRC 6ee4)
 st?=00
 
 s=01
 st?=00
 c=a8 (WRITE SECTOR, SINGLE RECORD, DONT CHECK SIDE, DAM=FB)
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 st?=00
 st?=00
 
 c=88 (READ SECTOR, SINGLE) /* verify */
 ?00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 st?=00
 
Next phase: Read all sectors of the disk, check whether there are bad sectors

 /* Check the rest of the sectors (2-359) */
 t=00
 d=00 
 s=02 (sector 2)
 t?=00
 st?=00
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 02 01 31 b7 (TRACK 0, SIDE 0, SECTOR 2, LENGTH 256, CRC 31b7)
 st?=00
 
 s=02 (sector 2)
 st?=00
 c=88 (READ SECTOR, SINGLE)
 ? ... (SECTOR CONTENT)
 
 t=00 (track 0)
 d=00
 s=03 (sector 3)
 t?=00
 st?=00
 c=c0
 ? 00 00 03 01 04 86 (TRACK 0, SIDE 0, SECTOR 3, LENGTH 256, CRC 0486)
 st?=00
 
 s=03
 st?=00
 c=88
 ? ... (SECTOR CONTENT)
 
 t=00
 d=00
 s=04 (sector 4)
 t?=00
 st?=00
 c=c0
 ? 00 00 04 01 9e 30 (TRACK 0, SIDE 0, SECTOR 4, LENGTH 256, CRC 9e30)
 st?=00
 
 s=04 
 st?=00
 c=88
 ? ... (SECTOR CONTENT)
 
 ... (skipping) ...
 
 t=27 (track 39)
 d=27
 s=06 (sector 6)
 t?=27
 st?=00
 c=c0
 ? 27 00 06 01 6f a0 (TRACK 39, SIDE 0, SECTOR 6, LENGTH 256, CRC 6fa0)
 st?=00
 
 s=06
 st?=00
 c=88
 ? ... (SECTOR CONTENT)
 
 t=27
 d=27
 s=07 (sector 7)
 t?=27
 st?=00
 c=c0
 ? 27 00 07 01 5a 91 (TRACK 39, SIDE 0, SECTOR 7, LENGTH 256, CRC 5a91)
 st?=00
 
 s=07
 st?=00
 c=88
 ? ... (SECTOR CONTENT)
 
 t=27 
 d=27
 s=08 (sector 8)
 t?=27
 st?=00
 c=c0
 ? 27 00 08 01 6a ed (TRACK 39, SIDE 0, SECTOR 8, LENGTH 256, CRC 6aed)
 st?=00
 
 s=08
 st?=00
 c=88
 ? ... (SECTOR CONTENT)

Return to sector 0, write the updated allocation bitmap.
 
 /* Write the VIB */
 t=27
 st?=00
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=25
 st?=24
 st?=24
 
 d=00
 s=00
 t?=00
 st?=24
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 00 01 5b d5 (TRACK 0, SIDE 0, SECTOR 0, LENGTH 256, CRC 5bd5)
 st?=00
 
 s=00 (sector 0)
 st?=00
 
 c=a8 (WRITE SECTOR, SINGLE RECORD, DONT CHECK FOR SIDE, DAM=FB)
 4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b 
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
 st?=00
 st?=00
 
 c=88 (READ SECTOR, SINGLE)  /* verify */
 ?4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 st?=00

Done: Get the disk information a last time and display it on the screen.
 
 /* Load VIB and FDIR for display on the screen */
 
 t=00 (track 0)
 st?=00
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=05
 st?=04
 st?=04
 
 d=00
 s=00 (sector 0)
 t?=00
 st?=04
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 01 01 6e e4 (TRACK 0, SIDE 0, SECTOR 1, LENGTH 256, CRC 6ee4)
 st?=00
 
 s=00
 st?=00
 c=88 (READ SECTOR, SINGLE)
 ?4c 45 45 52 34 20 20 20 20 20 01 68 09 44 53 4b
 20 28 01 01 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
 st?=00
 
 t=00 (track 0)
 st?=00
 c=0a (RESTORE, LOAD HEAD, NO VERIFY, 20ms@1Mhz)
 st?=05
 st?=05
 st?=04
 st?=04
 
 d=00 
 s=01 (sector 1)
 t?=00
 st?=04
 c=c0 (READ ADDRESS, NO DELAY)
 ? 00 00 01 01 6e e4 (TRACK 0, SIDE 0, SECTOR 1, LENGTH 256, CRC 6ee4)
 st?=00
 
 s=01
 st?=00
 c=88 (READ SECTOR, SINGLE)
 ?00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 st?=00
 
 c=d0
 st?=00
 
 END